1. Field of the Invention
The present invention relates to a nonvolatile memory device which utilizes a residual polarization in ferroelectrics to store information in a nonvolatile manner and to a method of manufacturing such a nonvolatile memory device.
2. Description of the Related Art
It has been proposed that an MFSFET (Metal Ferroelectric Semiconductor Field Effect Transistor) which is a kind of a field effect transistor having a ferroelectric gate film should be used in designing and fabricating a nonvolatile memory device.
FIG. 4 is a sectional view illustrating a configuration of an MFSFET used for storing information "1" or "0". Close to a surface of a P-type semiconductor substrate 1, an N.sup.+ -type drain region 3 and an N.sup.+ -type source region 4 are formed at a certain interval. A region between the drain region 3 and the source region 4 is to act as a channel region 2. On the channel region 2, a gate electrode 6 is provided with a ferroelectric gate film 5 sandwiched between them.
FIG. 5 is a graph illustrating a hysteresis loop of a polarization P in ferroelectrics related to an electric field E. In FIG. 5, a vertical axis represents the polarization P while a horizontal axis represents the electric field E. With reference to the P-E hysteresis loop, the theory of writing, erasing or reading information in or from the MFSFET in FIG. 4 will be described.
In writing information "1" in the MFSFET, ground potential is applied to the substrate 1, and programming voltage sufficiently larger than coercive voltage to the gate electrode 6. "Coercive voltage" means a voltage to obtain a coercive electric field Ec required to remove a residual polarization from the ferroelectrics. In this situation, the ferroelectric gate film 5 is polarized along an electric field applied between the gate electrode 6 and the substrate 1, assuming a state at point P1 in FIG. 5. This causes electrons to be induced to and around a surface of the channel region 2, and consequently, a channel electrically connecting the drain region 3 and the source region 4 is formed. After that, when the programming voltage is removed, the polarization in the ferroelectric gate film 5 exhibits a state at point Q1 in FIG. 5; that is, the polarization stays almost unchanged with the channel left as it was. This is a condition where the information "1" is stored in the MFSFET.
In erasing the information "1" from the MFSFET, or otherwise storing the information "0" therein, contrary to the writing, the ground potential is applied to the substrate 1 while the negative programming voltage sufficiently larger in absolute value than the coercive voltage to the gate electrode 6. At this time, an electric field almost a reversal to that which is applied in the writing, is applied to the ferroelectric gate film 5. This application of the electric field causes the polarization in the ferroelectric gate film 5 to invert into a state at point R1. After that, when the programming voltage is eliminated, the polarization in the ferroelectric gate film 5 varies into a state at point S1; that is, the previous state of the polarization is retained almost unchanged. This causes holes to be induced in the surface of the channel region 2, and therefore, the drain region 3 and the source region 4 stay electrically disconnected. This is a condition where the information "0" is stored in the MFSFET.
The information stored in the MFSFET can be read by examining whether the drain region 3 and the source region 4 are electrically connected or disconnected. For example, current is first supplied to the source region 4, and thereafter, by examining if this current can be detected in the drain region 3, the information stored can be identified with "1" or "0".
FIG. 6A is a circuit diagram showing a circuit structure of a nonvolatile memory where the MFSFET is utilized. The nonvolatile memory includes a memory cell array A where memory cells MC(m, n-1), MC(m, n), MC(m, n+1), MC(m+1, n-1), MC(m+1, n), MC(m+1, n+1) and so forth, are arranged in a matrix manner on a semiconductor substrate, and each cell can store binary data. Each of the memory cells MC(m, n-1), MC(m, n), MC(m, n+1), MC(m+1, n-1), MC(m+1, n), MC(m+1, n+1) and so forth, is formed of a couple of FETs, namely, one of information storing MFSFETs 10(m, n-1), 10(m, n), 10(m, n+1), 10(m+1, n-1), 10(m+1, n), 10(m+1, n+1) and so forth, mated with a corresponding one of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 11(m, n-1), 11(m, n), 11(m, n+1), 11(m+1, n-1), 11(m+1, n), 11(m+1, n+1) and so forth. Hereinafter, the memory cells MC(m, n- 1), MC(m, n), MC(m, n+1), MC(m+1, n-1), MC(m+1, n), MC(m+1, n+1) and so forth, are referred to as "memory cell(s) MC" en bloc, the MFSFETs 10(m, n-1), 10(m, n), 10(m, n+1), 10(m+1, n-1), 10(m+1, n), 10(m+1, n+1) and so forth, are referred to as "MFSFET(s) 10" en bloc, and MOSFETs 11(m, n-1), 11(m, n), 11(m, n+1), 11(m+1, n-1), 11(m+1, n), 11(m+1, n+1) and so forth, are referred to as "MOSFET(s) 11" en bloc.
Each MFSFET 10 has its drain connected to a source of the corresponding MOSFET 11. Rows of the MFSFETs 10 have their respective gates connected to a row decoder 12 via common word lines WLn-1, WLn, WLn+1 and so forth. Rows of the MOSFETs 11 have their respective gates connected to common selection control lines SLn-1, SLn, SLn+1 and so forth. Furthermore, Columns of the MOSFETs 11 have their respective drains connected to a column decoder 13 via common data lines DLm-1, DLm, DLm+1 and so forth. Reference numeral 14 designates a sense amplifier.
Referring to FIG. 6A, the writing of information in the memory cell MC(m, n) alone will now be described.
In order to write information merely in the memory cell MC(m, n), it is necessary to apply programming voltage V.sub.pp sufficiently larger than the coercive voltage only between the gate and drain of the MFSFET 10(m, n). For that purpose, the programming voltage V.sub.pp is applied to the word line WLn alone by the row decoder 12, voltage V.sub.dd at a fixed level which allows the MOSFETs 11 to turn on is applied to the selection control line SLn alone, and the ground potential equivalent to a potential of the semiconductor substrate is applied to the data line DLm. Programming inhibiting voltage Vi (.apprxeq.V.sub.pp /2) is applied to all the data lines DLm-1, DLm+1 and so forth, but the data line DLm. This causes the ferroelectric gate film in the MFSFET 10(m, n) to be polarized in a direction from a gate electrode towards the semiconductor substrate. In this way, the information "1" is written in the memory cell MC(m, n).
Then, the erasing of the information "1" alone from the memory cell MC(m, n), or the storing of the information "0" therein will be described with reference to FIG. 6B. An arrangement of a memory cell array A and other components shown in FIG. 6B is similar to that of FIG. 6A.
In order to erase only the information "1" from the memory cell MC(m, n), voltage reverse to that used in writing must be applied only between the gate and drain of the MFSFET 10(m, n). For that purpose, the programming voltage V.sub.pp is applied only to the data line DLm, and the voltage V.sub.dd is applied only to the selection control line SLn. Then, ground potential equivalent to that at the substrate is applied to all the word lines WLn-1, WLn, WLn+1, and so forth. This causes a direction of the polarization in the ferroelectric gate film to be inverted. In this way, the information stored in the memory cell MC(m, n) is loaded with "0" instead of "1", and thus, the erasing of the information "1" is effected.
Next, the reading of merely the information stored in the memory cell MC(m, n) will be explained with reference to FIG. 6C. An arrangement of a memory cell array A and other components shown in FIG. 6C is similar to that of FIG. 6A.
In reading merely the information stored in the memory cell MC(m, n), voltage at a fixed level is applied between the source and drain of the MFSFET 10(m, n). In this situation, examining if current flows between the source and drain, or if a channel is formed, the information "1" or "0" can be identified in reading.
More specifically, the voltage V.sub.dd is applied only to the selection control line SLn, and the voltage V.sub.dd is applied via a resistance 15 to the data lines DLm-1, DLm, DLm+1, and so forth. The ground potential is applied to the source of the MFSFET 10(m, n). Accordingly, the MOSFET 11(m, n) turns on, and there lies a potential difference of V.sub.dd between the source and drain of the MFSFET 10(m, n). If the memory cell MC(m, n) is loaded with the information "1", a channel is formed between the source and drain of the MFSFET 10(m, n). This allows current to flow from the data line DLm into the MOSFET 11(m, n) and the MFSFET 10(m, n). This current causes voltage drop in the resistance 15, and accordingly, a potential at the data line DLm drops to the level of the ground potential.
If the memory cell MC(m, n) is loaded with the information "0", no channel extends between the source and drain in the MFSFET 10(m, n). In this situation, no current flows into the data line DLm, and no voltage drop arises in the resistance 15. Thus, the potential at the data line DLm is retained at the level of V.sub.dd.
The column decoder 13 applies only the potential at the data line DLm to the sense amplifier 14, which, in turn, amplifies the potential at the data line DLm, and detects the resultant potential. In this way, the reading of data stored in the memory cell MC(m, n) is effected.
If the column decoder 13 selects any data line one after another, data can be sequentially read from the memory cells MC(m, n), MC(m+1, n) and so forth arranged in a row. Moreover, if a sense amplifier is provided for each of the data lines, data can be read at one time in parallel from all memory cells MC(m, n), MC(m+1, n) and so forth arranged in a row.
In recent years, as the semiconductor industry has increasingly advanced, demand for enhanced integration of a nonvolatile memory is raised. As a reaction to this, there may be proposed an enhancement of integration of a memory cell array. As to the memory cell array as shown in FIGS. 6A to 6C, however, it contains two transistors per cell, and such a memory cell array is not suitable for enhancement of the integration.
Then proposed is a memory integrated circuit having a configuration where a single cell has a single transistor, as shown in FIG. 7. In such a memory cell array, memory cells A, B, C, D and so forth, arranged in a matrix manner include respective MFSFETs 20A, 20B, 20C, 20D and so forth. The MFSFETs 20A, 20B, 20C, 20D and so forth, have their respective gates connected to word lines 21A, 21B and so forth, respectively, their respective sources connected to data lines 22A, 22B and so forth, respectively, and their respective drains connected to drain lines 23A, 23B and so forth, respectively.
When information stored in the memory cell A is read, for example, ground potential is applied to all the word lines 21A, 21B and so forth, and current is supplied only to the data line 22A. Furthermore, the ground potential is applied to the drain line 23A, and a potential identical to that at the data line 22A is applied to the remaining drain lines 23B and so forth. In this situation, it can be judged whether the MFSFET 20A is loaded with information "1" or "0" depending upon if the potential at the data line 22A drops; since the MFSFET 20A is in its ON-state when the MFSFET 20A stores the information "1", the potential at the data line 22A drops. Meanwhile, since the MFSFET 20A is in its OFF-state when the MFSFET 20A stores the information "0", the potential at the data line 22A never drops.
In the case where the memory cell A stores the information "0" while the remaining memory cells B, C and D respectively store the information "1", i.e., the MFSFET 20A is in its OFF-state while the remaining MFSFETs 20B, 20C and 20D, are in ON-state, the potential at the data line 22A drops regardless of the memory cell A loaded with the information "0". This is because, in such a condition, the data line 22A is electrically connected through a path P to the drain line 23A to which the ground potential is applied. Thus, the current supplied to the data line 22A flows as leakage current through the path P into the drain line 23A, and eventually, the potential at the data line 22A drops.
As has been described, there arises the problem that the arrangement shown in FIG. 7 is incomplete to assuredly perform the reading operation.